1. Field of the Invention
The present invention relates generally to semiconductor memories, and, more particularly, to a dynamic random access memory (DRAM) employing a dual port memory cell that supports hidden refresh.
2. Description of the Related Art
Semiconductor memory devices have been well-known for many years. Such devices are typically one of two types: volatile memory devices, such as dynamic random access memories (DRAMs), and non-volatile memory devices, such as static random access memories (SRAMs). Non-volatile memory devices will normally store data for an indefinite period of time once the data has been written into the memory cells. The cells are designed such that the electrical charge placed in the cell will remain in the cell indefinitely under appropriate conditions. The indefinite storage of the electrical charge is an advantage of the non-volatile memories, however, the memory cell in such a device is generally fairly large as compared to the memory cell in a volatile memory, and the larger memory cells consume a larger space on the semiconductor die.
Volatile memory devices will store electrical charge only for a very short period of time, and the electrical charge in the cells must be periodically refreshed. This requirement of refreshing the electrical charge in each of the memory cells is a disadvantage of volatile memories, but the memory cell size in these devices is typically much smaller than the cell size in the non-volatile memories. This difference is cell sizes allows the placement of a much larger number of volatile memory cells within a given die space as compared to the number of non-volatile memory cells that can be placed within the same die space. In modern microcomputer applications, a large amount of random access memory is typically required or, at least, desired. Moreover, because of the desire for ever increasing data processing speeds, greater amounts of random access memory have been incorporated within the same die with logic circuitry. For example, modern microprocessors typically include a large amount of on-chip memory to serve as a cache. As the amount of memory in an array increases, the amount of time required to refresh all the memory cells in the array likewise increases, xe2x80x9cstealingxe2x80x9d time that might otherwise be used for xe2x80x9creadxe2x80x9d and xe2x80x9cwritexe2x80x9d operations.
Efforts have been made to develop a system that would allow DRAM devices to replace SRAM devices in various cache architectures. A primary goal in those efforts has been to support greater amounts of cache memory in a system while simultaneously reducing costs. Two requirements in such a system are that the DRAM cache handle its own refresh requirements and that the refresh operations be completely hidden, i.e., that the refresh operations are transparent to the user. Prior attempts to design cache parts with DRAM devices have never completely solved the hidden refresh problem. These attempts have included utilizing on-board SRAM to store either a single row of DRAM data or multiple rows of DRAM data such that whenever this data is addressed, the corresponding row or rows are freed to be refreshed. Most of these attempts have constrained the system in various ways and are not seen as supporting truly random access.
The present invention eliminates or, at least, reduces the aforementioned problems.
The present invention is directed to an integrated circuit device having a memory cell for storing a data and refresh circuitry for refreshing that data in the memory cell. In one illustrative embodiment, the device comprises a memory cell having a storage element, a read/write access device, and a refresh access device. A read/write digit line is coupled to the read/write access device, and a refresh digit line is coupled to the refresh access device. A sense amplifier is coupled to the read/write digit line, and input/output circuitry is coupled to the read/write digit line. A refresh sense amplifier is coupled to the refresh digit line. The invention may be implemented in an integrated circuit memory device, or it may be combined with other semiconductor devices, either on a single semiconductor chip, within a single integrated circuit package, or in separate integrated circuit packages interconnected by means of other electrical circuitry.
In another aspect of the invention, a method of operating an integrated circuit device comprises coupling a memory cell to a first digit line, writing a data into the memory cell through the first digit line, de-coupling the memory cell from the first digit line, coupling the memory cell to a second digit line, refreshing the data in the memory cell through the second digit line, de-coupling the memory cell from the second digit line, coupling the memory cell to the first digit line, reading the data in the memory cell through the first digit line, de-coupling the memory cell from the first digit line, and periodically coupling the memory cell to the second digit line, refreshing the data in the memory cell through the second digit line, and de-coupling the memory cell from the second digit line.
In yet another aspect of the invention, a semiconductor memory cell comprises a charge storage element, a first access transistor coupled to the charge storage element and adapted to couple the charge storage element to a read/write digit line, and a second access transistor coupled to the charge storage element and adapted to couple the charge storage element to a refresh digit line. The first access transistor has a gate terminal coupled to a read/write word line, and the second access transistor has a gate terminal coupled to a refresh word line.
In yet another aspect of the invention, a semiconductor memory cell comprises a substrate and a serpentine active area in the substrate. First and second parallel digit lines overlap first and second regions, respectively, of the serpentine active area. First and second parallel word lines extend substantially orthogonally to the first and second parallel digit lines and overlap third and fourth regions, respectively, of the serpentine active area. A generally rectangular capacitor structure is parallel to and overlaying a fifth region of the serpentine active area between the first and second word lines.